1. Technical Field
The present invention relates to a semiconductor device.
2. Related Art
In recent years, with an increase in performance of semiconductor devices, insulating film formation technology, so called as a “low dielectric constant insulating film (referred to as low-k film) whose relative dielectric constant is lower than that of SiO2,” has been introduced in a semiconductor wafer diffusion process. There are many types of “low-k films”, adhesiveness and mechanical strength thereof are generally poor. Therefore, there is a problem in that a crack generated when dicing a wafer reaches a circuit forming region and exerts a harmful influence on the circuit forming region.
Japanese Laid-open Patent Publication No. 2006-5288 discloses a technology for forming a dummy via in each layer on the dicing region side. With this technology, even a crack is generated during dicing, the dummy via can prevent the crack from being propagated to a seal ring.
Japanese Laid-open Patent Publication No. H06-5701 discloses a procedure in which a plurality of grooves are formed on both sides of a scribe line, cutting grooves are formed conforming to the scribe line, and a wafer is divided. In addition, Japanese Laid-open Patent Publication No. H09-306872 discloses a configuration in which a chipping prevention portion composed of double grooves of a first groove and a second groove is provided in a scribe line region formed between a plurality of semiconductor chip regions on a semiconductor wafer.
However, when adhesion strength of the low-k film lowers, the size of chipping fragments increases. When the size of the chipping fragments increases, even the grooves are provided as disclosed in Japanese Laid-open Patent Publication No. H06-5701 and Japanese Laid-open Patent Publication No. H09-306872, the chipping fragments are forced in toward inside of the chip, cross the groove, and come into contact with an inside film of the groove by abrasive water during the dicing. At this time, the chipping fragments are in contact with the inside film while containing high pressure abrasive water and Si fragments during the dicing; and therefore, an inside film of the chip is damaged. If the crack is remained in the inside film of the chip, it becomes a failure in assembling and its assembling yield is lowered.
In addition, as disclosed in Japanese Laid-open Patent Publication No. 2006-5288, if it is configured that the dummy via is formed over the whole layers, there arises a problem in that it is difficult to release crack propagation. A mechanism of this problem will be described below with reference to FIGS. 14 and 15.
In FIG. 14, a semiconductor device 200 has a multilayer structure in which insulating layers laminated in the order of a stopper insulating film 202, a low dielectric constant insulating film 204, and a protective insulating film 206 are laminated in a plural number. In the semiconductor device 200, a dummy via 208 is formed over the whole layers of the multilayer structure. Impact and crack during the dicing are propagated from the scribe line toward inside of the chip. At this time, generally, as shown in FIG. 14, the impact and crack are propagated as boundary separation 210 between a low dielectric constant insulating film 204 which is weak in adhesion strength and a stopper insulating film 202 located at an under layer of the low dielectric constant insulating film. When the boundary separation 210 is propagated to the dummy via 208, the boundary separation is converted to boundary separation 210′ between the dummy via 208 and the low dielectric constant insulating film 204 and impact propagation 212 into the inside of the dummy via 208, as shown in FIG. 15.
At this time, if the dummy via 208 is too long, there is no place where the impact is released; and the impact propagation 212 into the inside of the dummy via 208 is progressed more dominantly than the boundary separation 210′. As a result, as shown in FIG. 16, a metal rupture 214 is generated. Then, as shown in FIG. 17, boundary separation 216 between the low dielectric constant insulating film 204 and the stopper insulating film 202 located at the under layer of the low dielectric constant insulating film is propagated on the inner side of the chip than the dummy via 208. If the boundary separation 216 stops in midstream, the stress is remained; and when assembling is made under this state, the separation is further progressed by thermal stress to lead occurrence of assembling failure.